Referring to FIG. 1, an exemplary magnetic storage system 100 such as a hard disk drive is shown. A buffer 102 stores data that is associated with control of the hard disk drive. The buffer 102 may employ SDRAM or other types of low latency memory. A processor 104 performs processing that is related to the operation of the hard disk drive. A hard disk controller (HDC) 106 communicates with the buffer 102, the processor 104, a host 108 via an I/O channel 110, a spindle/voice coil motor (VCM) driver 112, and a read/write channel circuit 114.
During a write operation, the read/write channel circuit 114 encodes the data to be written onto the storage medium. The read/write channel circuit 114 processes the signal for reliability and may include, for example, error checking and correcting coding (ECC) and run length limited coding (RLL). During read operations, the read/write channel circuit 114 converts an analog output from the medium to a digital signal. The converted signal is then detected and decoded by known techniques to recover the data written on the hard disk drive.
One or more hard drive platters 116 include a magnetic coating that stores magnetic fields. The platters 116 are rotated by a spindle motor that is schematically shown at 118. Generally, the spindle motor 118 rotates the hard drive platters 116 at a fixed speed during read/write operations. One or more read/write arm(s) 120 move relative to the platters 116 to read and/or write data to/from the hard drive platters 116. The spindle/VCM driver 112 controls the spindle motor 118, which rotates the platters 116. The spindle/VCM driver 112 also generates control signals that position the read/write arm 120, for example using a voice coil actuator, a stepper motor, or any other suitable actuator.
A read/write device 122 is located near a distal end of the read/write arm 120. The read/write device 122 includes a write element such as an inductor that generates a magnetic field. The read/write device 122 also includes a read element (such as a magneto-resistive (MR) sensor) that senses the magnetic fields on the platter 116. A preamplifier (preamp) circuit 124 amplifies analog read/write signals. When reading data, the preamp circuit 124 amplifies low level signals from the read element and outputs the amplified signal to the read/write channel circuit 114. While writing data, a write current that flows through the write element of the read/write channel circuit 114 is switched to produce a magnetic field having a positive or negative polarity. The positive or negative polarity is stored by the hard drive platter 116 to represent data.
Referring now to FIG. 2, an exemplary circuit 140 is presented that amplifies a signal across a variable resistance 142. This circuit could be used in the preamplifier of a magnetic storage system where the variable resistance is the MR sensor. A first current source 144 communicates with a supply potential 146. A second current source 148 communicates with a ground potential 150. The first and second current sources 144 and 148 communicate with a first terminal and an opposite terminal of a variable resistance 142, respectively. The first terminal of a variable resistance 142 communicates with a first terminal of a first capacitance 152. The opposite terminal of the variable resistance 142 communicates with a first terminal of a second capacitance 154.
A second terminal of the first capacitance 152 communicates with a noninverting input of a differential operational amplifier (op-amp 156). A second terminal of the second capacitance 154 communicates with an inverting terminal of the op-amp 156. The first terminal of the first capacitance 152 communicates with a first terminal of a first resistance 158. An opposite terminal of the first resistance 158 communicates with a first terminal of a third capacitance 160. A second terminal of the third capacitance 160 communicates with a noninverting output of the op-amp 156. The first terminal of the second capacitance 154 communicates with a first terminal of a second resistance 162. An opposite terminal of the second resistance 162 communicates with a first terminal of a fourth capacitance 164. A second terminal of the fourth capacitance 164 communicates with an inverting output of the op-amp 156.
Traditionally, the third and fourth capacitances 160 and 164 have been included to block DC current from flowing through the first and second resistances 158 and 162, respectively. These error currents would then flow through the variable resistance 142, causing its bias current to differ from what the first and second current sources 144 and 148 establish. Also, the current pulled from the output of the op-amp 156 by the first and second resistances 158 and 162 would affect the op-amp's performance. However, the third and fourth capacitances 160 and 164 create low-pass filters that interact with the high-pass filters created by the first and second capacitances 152 and 154, making the overall frequency response of the circuit difficult to design.